// 2-to-4 Line Decoder: Structural Verilog Desc.         //1
// (See Figure 4-10 for logic diagram)                   //2
module decoder_2_to_4_st_v(EN, A0, A1, D0, D1, D2, D3);  //3
   input EN, A0, A1;                                     //4
   output D0, D1, D2, D3;                                //5
                                                         //6
   wire A0_n, A1_n, N0, N1, N2, N3;                      //7
   not                                                   //8
      go(A0_n, A0),                                      //9
      g1(A1_n, A1);                                     //10
   and                                                  //11
      g3(N0, A0_n, A1_n),                               //12
      g4(N1, A0, A1_n),                                 //13
      g5(N2, A0_n, A1),                                 //14
      g6(N3, A0, A1),                                   //15
      g7(D0, N0, EN),                                   //16
      g8(D1, N1, EN),                                   //17
      g9(D2, N2, EN),                                   //18
      g10(D3, N3, EN);                                  //19   
endmodule                                               //20